1. Field
Exemplary embodiments of the present invention relate to a memory and a memory system including the same.
2. Description of the Related Art
A memory cell of a memory includes a transistor serving as a switch and a capacitor that store a charge (data). Depending on whether charge is stored in the capacitor of the memory cell, that is, whether a terminal voltage level of the capacitor is high or low, the data may be identified as high (logic 1) or low (logic 0) data.
Data is stored in a capacitor and no power is consumed in theory. However, since leakage current leakage in the PN junction of the MOS transistor as well as other places, the initial charge accumulated in the capacitor may decrease and data may be lost. In order to prevent data loss, data of the memory cell must be read and the charge in the capacitor must be refreshed. This is called a refresh operation
FIG. 1 is a diagram illustrating part of a cell array included in a memory that will be used to explain a phenomenon called word lime disturbance. In FIG. 1, BL represents a bit line.
Referring to FIG. 1, three word lines WLK−1, WLK, and WLK+1 in the cell array are arranged in parallel. Furthermore, the K-th word line WLK with notation “HIGH_ACT” has been has been activated numerous times (i.e. the activation frequency of the K-th word line WLK is high). The (K−1)th and (K+1)th word lines are adjacent to the active K-th word line WLK. Furthermore, (K−1)th, K-th and (K+1)th memory cells CELL_K−1, CELL_K, and CELL_K+1 are coupled to the (K−1)th, K-th and (K+1)th word lines WLK−1, WLK, and WLK+1, respectively. The (K−1)th, K-th and (K+1)th memory cells CELL_K−1, CELL_K and CELL_K+1 include (K−1)th, K-th and (K+1)th cell transistors TR_K−1, TR_R, and TR_K+1 and K−1)th K-th and (K+1)th cell capacitors CAP_K−1, CAP_K and CAP_K+1 respectively.
When the K-th word line WLK is activated and precharged (deactivated), the voltages of the adjacent (K−1)th and (K+1)th word lines WLK−1 and WLK+1 fluctuate from coupling between the K-th word line WLK and the adjacent (K−1)th and (K+1)th word lines WLK−1 and WLK+1, thereby influencing charges stored in the (K−1)th and (K+1)th cell capacitors CAP_K−1 and CAP_K+1. Thus, when the K-th word line WLK is frequently activated-precharged to toggle between the active state and precharge state, data stored in the (K−1)th and (K+1)th memory cells CELL_K−1 and CELL_K+1 may be affected by the impact on charges stored in the (K−1)th and (K+1)th capacitors CAP_K−1 and CAP_K+.
Furthermore, electronic waves, which are generated while a word line toggles between the active state and the precharge state, may introduce/discharge electrons into/from a cell capacitor included in a memory cell coupled to an adjacent word line, thereby affecting the data of the memory cell.